1. Field of the Invention
The present invention generally relates to etching with high energy radiation or plasma, and more particularly, to a method and apparatus for controlling the etching rate at the edge of a wafer in an integrated semiconductor circuit manufacturing process.
2. Description of the Related Art
Since the mid-1960s, integrated semiconductor circuits have become the primary components of most electronics systems. These miniature electronic devices may contain thousands of the transistors and other circuits that make up the memory and logic subsystems of microcomputer central processing units. The low cost, high reliability, and speed of these computer chips has led them to become a ubiquitous feature of modem digital electronics.
The fabrication of an integrated circuit chip typically begins with a thin, polished slice of high-purity, single-crystal semiconductor material substrate (such as silicon or germanium) called a xe2x80x9cwafer.xe2x80x9d Each wafer is subjected to a sequence of physical and chemical processing steps that form the various circuit structures on the wafer. During the fabrication process, various types of thin films may be deposited on the wafer using various techniques such as thermal oxidation to produce silicon dioxide films, chemical vapor deposition to produce silicon, silicon dioxide, and silicon nitride films, and sputtering or other techniques to produce other metal films.
After depositing a film on the semiconductor wafer, the unique electrical properties of semiconductors are produced by substituting selected impurities into the semiconductor crystal lattice using a process called doping. The doped silicon wafer may then be uniformly coated with a thin layer of photosensitive, or radiation sensitive, material called a xe2x80x9cresist.xe2x80x9d Small geometric patterns defining the electron paths in the circuit may then be transferred onto the resist using a process known as lithography. During the lithographic process, the integrated circuit pattern may be drawn on a glass plate called a xe2x80x9cmaskxe2x80x9d and then optically reduced, projected, and transferred onto the photosensitive coating covering the resist.
The lithographed resist pattern is then transferred onto the underlying crystalline surface of the semiconductor material through a process known as etching. Traditional etching processes employed wet chemicals that proved to be limited in terms of the size and aspect ratio (i.e., the height to width ratio of the resulting notch) of the features that could be formed on the wafer. Consequently, the number of circuits that could be packed onto a single wet-etched wafer, and hence the ultimate size of the electronic device, were limited by traditional chemical etching processes.
Dry plasma etching, reactive ion etching, and ion milling techniques were later developed in order to overcome the limitations associated with chemical etching. Plasma etching, in particular, allows the vertical etch rate to be made much greater than the horizontal etch rate so that the resulting aspect ratio of the etched features can be adequately controlled. In fact, plasma etching enables very fine features with high aspect ratios to be formed in films approaching 1 micrometer in thickness.
During the plasma etching process, a plasma is formed above the masked surface of the wafer by adding large amounts of energy to a gas at low pressure. This is commonly accomplished by creating electrical discharges in gases at about 0.001 atmospheres. The resulting plasma may contain ions, free radicals, and neutral species with high kinetic energies. By adjusting the electrical potential of the substrate to be etched, the charged particles in the plasma can be directed to impinge upon the unmasked regions of the wafer and thereby remove atoms from the substrate.
The etching process can often be made more effective by using gases that are chemically reactive with the material being etched. So called xe2x80x9creactive ion etchingxe2x80x9d combines the energetic etching effects of the plasma with the chemical etching effect of the gas. However, many chemically active agents have been found to cause excessive electrode wear.
It is desirable to evenly distribute the plasma over the surface of the wafer in order to obtain uniform etching rates over the entire surface of the wafer. For example, U.S. Pat. Nos. 4,792,378 and 4,820,371 to Rose et al. disclose a shower head electrode for distributing gas through a number of holes in the electrode. These patents generally describe a gas dispersion disk having an arrangement of apertures which is tailored to the particular pressure gradients existing within a reactor chamber in order to provide a uniform flow of gas vapors to a semiconductor wafer. The gas dispersion disk is intended to function as a selective barrier to counteract gradient pressures below the disk and to provide a uniform flow through the shower head electrode for distribution over the entire surface of the wafer. Any discontinuities or irregularities in the plasma discharge system, such as pumping ports, may also affect the density of the plasma being generated below the showerhead.
Since the integrated circuit fabrication process is quite sensitive to both particulate and impurity contamination, even airborne particulate matter as small as 1 micrometer must be prevented from contacting the surface of the wafer during the etching process. Consequently, it is often desirable to confine the plasma to the area which is immediately over and around the wafer substrate. For example, Sakata et al. (U.S. Pat. No.4,610,774) discloses an annular wall around a sputtering target that can repulse, and return toward the center, those electrons which tend to escape from the plasma during the sputtering process. Similarly, Ishii et al. (U.S. Pat. No. 5,571,366) disclose a gas supplying means for a plasma processing apparatus having an annular projection around the perimeter thereof which operates to concentrate a gas to the target surface of the object to be processed. Maydan et al. (U.S. Pat. No.5,643,394) disclose a plasma chamber lid having an annular reflector designed to focus an injected gas toward the center of a wafer being processed.
Plasma processing is typically conducted in a parallel plate reactor apparatus wherein the reactor volume is defined by a pair of closely spaced electrode plates. Examples of parallel plate plasma processing reactors for processing semiconductor substrates such as silicon wafers are disclosed in U.S. Pat. Nos. 4,960,488; 5,074,456; 5,569,356; and 6,073,577. The use of planar electrodes in a parallel plate plasma reactor, however, can result in a non-uniform plasma density across the surface of the substrate. Typically, the plasma density in the region near the edge of the substrate is less than that at the center. Thus, using a conventional parallel plate reactor in a plasma etching process can result in reduced etch rates near the edge of the substrate being processed.
Shaped electrodes have been disclosed to improve uniformity in plasma processes. See, for example, Mundt et al. (U.S. Pat. No. 4,297,162), Kim et al. (U.S. Pat. No. 5,990,016), Mallon (U.S. Pat. No.5,628,869), Donohue et al. (U.S. Pat. No. 6,010,636), Salimian (U.S. Pat. No.5,716,485), Zajac (U.S. Pat. No. 4,230,515). See also two commonly owned patents issued to Mundt et al. (U.S. Pat. No.5,472,565 and U.S. Pat. No. 5,714,031).
The present invention provides an electrode for use in a plasma reaction chamber. The electrode has a central portion including plurality of gas outlets through which process gas can be delivered from an exposed surface of the electrode. A step is located in a peripheral portion of the electrode and extends at least partially around the central portion of the electrode. The step can enhance the density of the plasma formed adjacent the exposed surface of the electrode. The central portion of the electrode can be substantially planar. In a preferred embodiment, the step is located inwardly of an outer periphery of the electrode such that the electrode extends beyond the step.
The present invention also provides a method of treating a semiconductor substrate in a plasma chamber. The method comprises: supporting a substrate on a bottom electrode; supplying a process gas to the chamber; forming a plasma adjacent an exposed surface of an upper electrode; and processing the semiconductor substrate with the plasma. The upper electrode has a central portion and a peripheral portion which includes a step projecting from an exposed surface thereof and extending at least partially around the central portion. The step provides a predetermined localized plasma density adjacent the exposed surface of the electrode. The upper electrode can be a showerhead electrode having a central portion with one or more gas outlets for discharging the process gas into the chamber.
The present invention also provides a plasma chamber for use in manufacturing a semiconductor device. The plasma chamber includes a top electrode and a bottom electrode having respective surfaces facing each other and spaced apart from one another to define a gap therebetween. The bottom electrode comprises a substrate support. The top electrode includes a central portion and a step projecting from a peripheral portion thereof and extending at least partially around the central portion. The step affects the localized density of the plasma formed adjacent the exposed surface of the top electrode in the step region. The chamber can also include an edge ring mounted on the bottom electrode. The edge ring can act in conjunction with the step on the upper electrode to provide a predetermined localized plasma density adjacent the exposed surface of the electrode